A 6-page Technical Disclosure, plus 2-page Appendix, and thirteen (13) hand-drawn circuit/logic diagrams. Parity-checking is a paradigm in logic/data-processing circuitry to represent the odd or even count of the eight (8) "0 or 1" data bits, for example, of an 8-bit byte. A ninth bit - the parity bit - is a "1" if the "1" count within the 8-bit byte is 'odd', or is a "0" if the "1" bit count is even. This is known as an "odd" parity-bit generator; an even-bit parity generator would output a "0" bit for this example. This disclosure, authored by JVM, describes a general-case solution for a "2 to N bit-wide" word, employing MRC NOR-OR transistorized logic circuits. Developed in the early 1960's, long before integrated circuits were commonly available, this logic would fit in a tiny corner of an IC chip today